The present invention relates to a memory refresh circuit for refreshing a computer memory and more particularly to a memory refresh circuit which is adapted to be used in a processing system for storing information employed for arithmetic processing, such as program information, data employed for arithmetic operation, data resulting from arithmetic operations as well as data displayed on the screen of a display unit, in the same (common) memory.
With the advance of semiconductor technology, personal computers have become popular. Such computers contain built-in microprocessors and are suitable for personal use.
FIG. 1 is the typical structure of a personal computer in block diagram form.
The personal computer comprises a central processing unit (CPU) 101, a random access memory (RAM) 102 for storing the data to be processed by CPU 101, the result of arithmetic operations, etc., a read only memory (ROM) 103 for storing the processing procedure effected in CPU 101, data used only in reading, etc., a data bus 104 for transmitting the data to be processed in CPU 101, an address bus 105 for transmitting the addresses of units and memories to be accessed by CPU 101, an I/O interface circuit 108 connected to the data bus 104 and the address bus 105 for connecting input/output units such as a keyboard 106 and floppy disk drive (FDD) 107 to CPU 101, a video RAM (VRAM) 111 connected to the address bus 105 through a changeover switch 112 and storing graphic information to be output on a display 110, a display address signal generator 113 connected to VRAM 111 through the changeover switch 112 and generating the display addresses for sequentially reading the graphic information stored in VRAM 111, a display control circuit 115 connected to VRAM 111 through a data bus 114 and converting the graphic information sequentially read out of VRAM 111 to an image signal to be output on the display 110, a memory control circuit 116 for selectively connecting the changeover switch 112 to the address bus 105 when writing graphic information into VRAM 111 or to the display address signal generator 113 when making a display on the display 110, a data bus control circuit 117 for connecting data bus 104 to VRAM 111 when the memory control circuit 116 writes graphic information into VRAM 111, etc. In a personal computer of this type, data employed for arithmetic operation, programs prepared by users, etc. are stored in RAM 102, while the picture information employed for display is stored in VRAM 111. Accordingly, it requires two systems of random access memories, thereby increasing the cost.
For this reason, there has been proposed a method to integrate both VRAM 111 and RAM 102 into a common memory. The typical method is described in Japanese Patent Laid-Open No. 66022/1980. There will now be explained the prior art in which the random access memory (RAM) 102 and the video random access memory (VRAM) 111 are both constituted in a common single memory, with reference to FIGS. 2-4.
The circuits shown in FIG. 2 comprise a central processing unit (CPU) 201, a display address signal generator 202 for generating display addresses necessary for display and various timing signals, a changeover switch 203 for switching over from the display addresses to the addresses from CPU or vice versa, a memory control circuit 204, a common memory 205 serving as both a system memory and a display memory, a data bus control circuit 206, a display control circuit 207, a display 208 typically formed of a cathode-ray tube, a data bus 209 for transmitting data between CPU 201 and the respective circuits, an address bus 210 for supplying an address signal, to be accessed by CPU 201, to the respective circuits, an address line 211 for sending the display addresses to indicate relative positions on the display screen, a signal line 212 for sending a signal indicating the display time, a signal line 213 for sending various synchronizing signals to the display, i.e., horizontal synchronizing signal, vertical synchronizing signal, etc., a signal line 214 for sending a switching signal to switch over the changeover switch 203 from the addresses from transmitting CPU 201 to transmitting the display addresses or vice versa, a signal line 215 for sending a control signal applied to the data bus control circuit 206, a signal line 216 for sending a control signal applied to the memory 205, a changeover switch 217 for connecting the memory 205 to the display control circuit 207 only when display data is read out of the memory 205, a signal line 218 for supplying a switching signal to the changeover switch 217.
FIG. 3 is an example of allocation of the common memory 205. Addresses are expressed in hexadecimal notation.
The region of addresses 0000-0500 is a work memory area which is used by CPU at the time of calculation. The region of addresses 0501-43FF is a display memory area for storing therein display data. In other words, this memory area is used for the same purpose as the video random access memory (VRAM) in the circuitry of FIG. 1. The region of addresses 4401-9FFF is a user RAM area which can be employed freely by users and in which various data, programs prepared by users, etc. are stored. The region of addresses A000-FFFF is a ROM area which functions similarly to a read only memory (ROM). This area stores therein a compiler program, an interpreter program or programs and data for supervising an operating system and computer system.
It is to be noted herein that the areas other than the display memory area are together referred to as a system memory, because they are used by the computer in arithmetic processing.
FIG. 4 shows a relationship between the horizontal scanning time and the vertical scanning time in the display, when information is displayed using the circuitry of FIG. 2. As shown in FIG. 4, the total scanning time is divided into two parts; a display time 401 and a blanking time 402. During the display time 401, the display data are sequentially read out of the memory 205 and then indicated on the display 208. During the blanking time 402, the changeover switch 203 is connected to the side of the address bus 210 to stop reading of the display data from the memory 205, thereby alternately transmitting data between the central processing unit (CPU) 201 and the system memory area in the memory 205, or rewriting data for the display memory area.
Operation of the circuitry shown in FIG. 2 will now be briefly described.
First, during the display time, the address changeover switch 203 is connected to the side of the display address line 211 and display addresses are applied to the memory 205 from the display address signal generator 202.
The display addresses output from the display address signal generator 202 are those corresponding to addresses of the display memory area in the memory 205 shown in FIG. 3, and these addresses correspond to positions on the screen of the display 208 in a one-to-one relation. In accordance with scanning of the display 208, the display addresses are sequentially supplied from the display address signal generator 202 to the memory 205, and display data, brightness, color, etc., corresponding to positions on the display screen are read out of the memory 205 to be supplied to the display control circuit 207. The display control circuit 207 generates an image signal indicating characters or figures corresponding to the display data supplied from the memory 205, and then supplies the image data to the display 208.
Coming into the blanking time, the address changeover switch 203 is connected to the side of the CPU address line 210 and an address signal from the CPU is applied to the memory 205. At this time, the data bus control, circuit 206 conducts and connects the data bus 209 to the memory 205, so that CPU 201 transmits and receives data to and from the memory 205 through the data bus 209.
This system is advantageous in that the circuit structure is relatively small, and also in that a dynamic RAM, much cheaper than a static RAM, can be used as the memory 205 without the need for providing a refresh circuit. Because a dynamic RAM stores information by utilizing a floating capacity in its internal gate, it tends to lose the content stored therein, if left as it is, from the fact that the electric charge accumulated in the gate is gradually reduced by leakage current through floating capacitance. To prevent the above tendency, the dynamic RAM generally requires a refresh circuit which periodically charges the gate capacity, the so-called "refresh" operation. In the above system, however, since the memory 205 is sequentially read for display in the display time, and since the refresh operation is performed simultaneously at that time, there is no need for providing a special refresh circuit.
But in such a system, data transmission between CPU 201 and the memory 205 is allowed only during blanking time, with a consequent low processing speed when the programs on the system memory are operated, or when the displayed content is changed.
For example, assuming that the display time and the blanking time are each given as 50% in FIG. 2, the average processing speed would be reduced by half. And if a dynamic random access memory DRAM is used as the memory 205, display reading must be made from the dynamic RAM to run the refresh operation for DRAM even in case of technical calculation, for example, which requires no display. Thus, processing speed is lowered independently of the presence or absence of display in the above-mentioned system, because data transmission between CPU 201 and memory 205 is not allowed during the display time.